VHDL: truth table in ieee std_logic library

Question

I looked into how IEEE defines its libraries. When I opened up stdlogic library, I saw a few truth tables that are defined as constant. I have no idea how the truth tables function. Please explain how the result is returned using truth table. Here is what I found for "AND" gate:

TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;

-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
--      ----------------------------------------------------
--      |  U    X    0    1    Z    W    L    H    -         |   |  
--      ----------------------------------------------------
        ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ),  -- | U |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | X |
        ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),  -- | 0 |
        ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | 1 |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | Z |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | W |
        ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),  -- | L |
        ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | H |
        ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )   -- | - |
);

FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
    RETURN (and_table(l, r));
END "and";

"UX01" is defined as

SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO 'Z';

I have no idea how the key word "resolved" is used. "resolved" is defined as a function in the library

FUNCTION resolved (s: std_ulogic_vector) RETURN std_ulogic;

I googled how the truth table functions for a while, but no luck to find a explanation. Please explain how the table evaluates the inputs. Thanks a lot

This question appears to be off-topic because it is about electrical engineering. You may be able to get help on http://electronics.stackexchange.com/ — Guy Sirton, Jul 21 '14 at 00:32
@GuySirton - It's a valid VHDL question on the subject of amongst others, resolution functions. Check out info for the VHDL tag. — , Jul 21 '14 at 01:20
You could note that for VHDL-2008 compliant tools the proper source for the std_logic_1164 package body is [1076-2008_machine-readable.zip](https://standards.ieee.org/downloads/1076/1076-2008/1076-2008_machine-readable.zip "1076-2008_machine-readable.zip") when unzipped, subdirectory ieee. — , Jul 21 '14 at 01:44
@DavidKoontz I interpret http://stackoverflow.com/help/on-topic as indicating that VHDL questions are off topic. VHDL is primarily used for describing/generating electrical circuitry. Since there is a stack exchange site dedicated to electrical engineering that would be a more appropriate place to ask VHDL questions. That's my opinion at least. Another example is that while one can use machines for computation asking mechanical engineering questions on this site is something that wouldn't be on topic. — Guy Sirton, Jul 21 '14 at 03:43
@GuySirton - If SO would change its braindead, fragmented login system some of us might be more active on the EE subdomain. As it stands the bulk of VHDL related questions are here so they get answered here. Furthermore, VHDL functions as a general purpose simulation language that performs tasks not directly implementable in hardware such as dynamic memory allocation and file I/O. Should other specialty languages like MATLAB be forced elsewhere too? — Kevin Thibedeau, Jul 21 '14 at 15:02
@KevinThibedeau There is an e.g. Mathematica SE. By your logic there should be only one SE site, SO, where you can ask any question on any topic. I have two issues: 1. VHDL is typically not used for software development 2. mixing VHDL questions with general software development questions propagates the misunderstanding that VHDL is somehow just another programming language. You haven't convinced me that it should be considered on topic. Simulation languages not related/used for software development are off topic as well. Probably a discussion for meta. — Guy Sirton, Jul 21 '14 at 17:42
SO and EE VHDL questions can be roughly separated by being about the language itself or using it to produce hardware, matching the difference between the two sites. There are gcc and llvm front-ends for VHDL. The first VHDL standard shared over 62 percent of it's text with the Ada 83 RM. A VHDL model is compiled (analyzed), linked (elaborated) and simulation is executing an elaborated model with the aid of a run time library (which can be interactive). All recent proposed standard changes emphasize general programming constructs and the standard itself doesn't specify any hardware. — , Jul 21 '14 at 19:25
At one time the ability to create a [hello world program](http://home.gna.org/ghdl/ghdl/The-hello-word-program.html "hello world program") in a language was sufficient to recognize it was a programming language. — , Jul 22 '14 at 04:26

score 2 · Answer 1 · 2014-07-21T17:45:39.163

The AND table replete with declarations you show is a two dimensional array, indexed by std_ulogic (enumerated) values. An AND function has a left and right argument (l and r), use to index a result in the table.

The table is shown as a 2D array to make it user readable, the intersection of a column comment enumerated value index and row comment enumerated value index indicating the result of a logical AND operation.

Resolution functions are a bit more complex and involve advanced reading either from the standard or various explanatory texts.

A resolution function is used to 'resolve' multiple drivers on a signal. The various driver values are organized as a vector with the length equal to the number of drivers, where after the first driver value being 'resolved' against a default driver (in this case see the package body of std_logic_1164, the default value for result is 'Z'), each successive driver is resolved by resolution table look up against the accumulated result.

The purpose is to determine the 'resolved' signal value of a signal having multiple drivers, in this case using the MVL9 (multi level logic with 9 levels) adopted as an IEEE Standard (IEEE Std 1164, now part of VHDL standard. It's part of the language (and not as Guy Sirton indicates solely an electrical engineering issue).

Setting up resolution occurs during elaboration it's a function of simulation.

Any two concurrent statements driving the same signal require resolution. Resolution occurs even with only one driver (against that default 'Z'). If you don't use resolved types you'll get an error message. If you use resolved types you'll get a resolution value and won't be protected against connecting multiple drivers to the same signal when perhaps you shouldn't be doing so.

addendum

One more question. To navigate through a 2D array, I thought we use array index. Like (1,2) = row 1, column 2. use how does and_table(U,1) matches up Row 1, Column 4 or Column 1 row 4? – Hong Pan 1 hour ago

The question and answer format isn't set up for 'One more question'.

The indexes are type std_ulogic, not numerical types. An enumerated type has a positional value that can be expressed as a numerical type. For std_ulogic enumeration values, the first value is 'U' the next is 'X',... on to '-'. To find a std_ulogic positional value you could use the 'POS attribute where std_ulogic'POS(l) will return an index position value for l. You can convert a universal integer number representing a positional value to a std_ulogic value by using the 'VAL attribute.

The index values l and r are used by convention to signify left and right operands to predefined binary operators. l AND r provides the two indexes as l and r.

FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
    RETURN (and_table(l, r));
END "and";

You're not allowed to specify a predefined operator with an interface list - AND(l,r). l is the second dimension, specifying rows while r specifies columns. And it doesn't matter in these cases, the tables work the same switching the two indexes.

Note the return value is a subtype (UX01) of std_ulogic and only those four values are found in the table.

And all of this can be discerned by the knowledgeable VHDL user from the the information you provided in your example. It speaks to the need for a a good text on the language or access to the standard (IEEE Std 1076-2008), wherein all answers can be found.

One more question. To navigate through a 2D array, I thought we use array index. Like (1,2) = row 1, column 2. use how does and_table(U,1) matches up Row 1, Column 4 or Column 1 row 4? — Hong Pan, Jul 21 '14 at 05:08

VHDL: truth table in ieee std_logic library

1 Answers1

Linked