verilog Linear feedback shift register random

Question

module do2(rst,clk,cout);
input rst,clk;
output [7:0]cout;
reg [2:0]D;
reg [19:0]count;


assign cout=out(D);
always@(posedge clk) begin
count = count+20'd1;
if(rst) begin
D<=3'b0;

end
else if(count==20'd100000)begin

D[0] <=D[1];
D[1] <=D[2];
D[2] <= D[0] ^D[2];
end
end

function [7:0]out;
input [2:0]in;


begin
case(in)
3'b000 : out =8'b11111100 ;
3'b001 : out =8'b01100000 ;
3'b010: out =8'b11011010 ;
3'b011 : out =8'b11110010 ;
3'b100 : out =8'b01100110 ;
3'b101 : out =8'b10110110 ;
3'b110 : out =8'b00111110 ;
3'b111 : out =8'b11100100 ;

endcase 
end

endfunction 
endmodule

I write the verilog programming code using QuartusII. I want to make a random number generation operation. Linear Feedback Shift Register is used to generate random number. But, I don't know why the random pattern is same. The result of operation like this 8 5 4 2 7 .... 8 5 4 2 7. How to solve these problem? Please refer your opinion.

Possible duplicate http://stackoverflow.com/questions/12632734/verilog-random-number-generator/12635496#12635496 and http://stackoverflow.com/questions/14800189/why-are-the-outputs-of-this-pseudo-random-number-generator-lfsr-so-predictable — e19293001, Dec 01 '15 at 09:10

score 5 · Accepted Answer · edited May 23 '17 at 12:15

A couple of mistakes in the design:

You have not initialized count variable here. Along with initializing D, count must be initialized. After count reaches 20'd100000, it must be reset or re-initialized. For next round of randomization.

In the always block, the condition if(rst) and else if(count..) can result into unintentional hardware. Adding else condition can remove in unwanted latch creation.

Also, initially, D<=3'b0 will have zero initial seed, and xoring operation shall also result in zero output (D[0]^D[2] = 0^0 = 0), so the output shall never change. I would prefer to use a parameter seed = 3'b000 which can easily be overridden while instantiation. Like folows:

parameter seed = 3'b000 // Arbitrary seed value
if(rst) begin
D<= seed;
count<=20'd0;
end

// While instantiation
do2 #(5) dd(rst,clk,cout);

I have provided a testbench at EDAPlayground here, with the above mentioned changes. Kindly go through it.

EDIT:

From the comment below, since there are three bits for flip flops, a maximum of eight states are possible, hence output can contain maximum of eight states (as e4 f2 da b6 60 66 3e). Increasing the number of flipflops, and conditions in case statements shall result in wide range of output values.

Refer to Pseudo Random Number Generation link for more robust LFSRs.

@e19293001 Oh I forgot to mention the main point. Thanks for the inputs, This is due to only three flops (maximum of 8 states) and 8-bit `cout`. This problem is resulting due to lesser number of flop states. I have edited my answer above. Thanks again. — sharvil111, Dec 01 '15 at 10:28

verilog Linear feedback shift register random

1 Answers1