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How is the coherence between the first level cache & register file is handled ?

To be specific, if the instruction has already fetched the data from memory & while executing the data is changed in the memory then processor would end up operating on stale data, so how does a processor realize this & compensate ?

username_4567
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  • It doesn't compensate. That's why `inc dword [mem]` is *not* atomic. The register file is in no way coherent with memory. – Peter Cordes Sep 24 '16 at 00:33
  • Possible duplicate of [Can num++ be atomic for 'int num'?](http://stackoverflow.com/questions/39393850/can-num-be-atomic-for-int-num) – Peter Cordes Sep 24 '16 at 00:33
  • Also related: [this Q&A about how out-of-order execution is different from memory ordering](http://stackoverflow.com/questions/39670026/out-of-order-instuction-execution-is-commit-order-preserved) – Peter Cordes Sep 24 '16 at 00:35

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