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I'm trying to read the Intel documentation on the CPU registers, and the question came up that I can't seem to find an answer to.

Say, all of the available registers:

  • GPR (general purpose registers)
  • Control Registers: RIP, EFLAGS, CR0-CR15, EFER, MSRs, etc.
  • GDTR, IDTR, TR, etc.

Are they all shared among multiple CPU cores, or are there copies of them specific for each core?

MikeF
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    Each core has their own, otherwise it would be impossible for them to execute independently. – Banex Jul 24 '18 at 08:33
  • @Banex: Thanks. But, for instance, what would happen if, say, I set up different interrupt descriptor table registers (with different IDT base pointers) for different cores. Will the same interrupt number be serviced by different procedures depending on which core receives the interrupt? – MikeF Jul 24 '18 at 08:36
  • @MikeF: Yes. I'm not sure if that's ever useful; more useful is steering one kind of interrupt more towards some cores and other kinds to other cores, so their handler code and associated data structures might stay hot in cache. But I think you do that with the APIC; you'd still normally want each core to share the same IDT. Unless maybe you had a per-core timer interrupt with the core number hard-coded as an immediate so each core would increment its own local counter. – Peter Cordes Jul 24 '18 at 13:01

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