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I'm pretty new to computer organization and systems so I apologize in advance if I say anything wrong. I'm learning about the MIPS architecture and I have a ton of questions about memory and addressing:

  1. So far, all I know is that when we have a 32-bit CPU, that means that we process data in 32 bit chunks. The CPU consists of the ALU and cache memory that comprises of 32 registers. The memory stores instructions that are 32 bits long. The way I visualise memory is that it is a rectangle with multiple rows, with each row being 32 bits long.
  2. Now, my question is related to how we address registers and memory. When we use the load word or store word commands, we call certain memory locations in order to store data in them, or to transfer data stored in them into a register present in the cache. I have come across terms such as $t0, $s0 etc. which I'm assuming are monikers for certain kinds of registers. My question is- How long are memory addresses in bits? For example, if we want to access data stored in row 1 of the memory, how long is the "address" of row 1? I read somewhere that the address itself is 32 bits long, and this 32 bit address in turn refers to data that is 32 bits long. Does this mean that there are 2^32 possible addresses or rows of memory, with each address storing 32 bits of data?
  3. Now if the above is true, I assumed that registers also have addresses that are 32 bits long, but then I realized that in MIPS there are only 32 registers, which means that each register address is 5 bits long, and each 5-bit address points to 32-bit long data. In that case, are register addresses and memory addresses of different lengths, i.e. 5bits and 32 bits respectively?
  4. My final confusion is related to the difference between byte addressability and word addressability. If data is byte addressable, that means that every byte has its own address. Does this mean that the 2^32 memory locations I spoke about earlier point to data that is 8 bits long and not 32 bits long? Similarly, in the case of registers, does every byte of the 32 registers have its own address? Which means that there are 4*32 unique addresses for each byte? In that case, it contradicts the fact that 5 bits are used to store the address. As you can see, I'm extremely confused and would appreciate all the help I can get.
Peter Cordes
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anonimousse
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  • We basically don't address registers in software. We can name registers in instructions, but there is no simple notion of *a variable that is a reference to a register* that can easily obtain a register's value in software. Whereas with memory we can do addressing: we can have a variable that hold a reference to memory (called a pointer), and use such variables to easily access the memory they refer to (using loads and stores). So, we name registers in instructions, but we don't index them as if an array or as if memory. – Erik Eidt Sep 23 '21 at 16:34
  • To understand the registers we look at the fields of the instructions, e.g. in an R-Type instruction, three registers are specified, using 5-bit fields for each. While memory is either little or big endian (from being byte addressable) we cannot tell whether the 32-bit registers are big or little endian, since we can only name (whole) registers in instructions (and otherwise cannot access them e.g. by some kind of reference). – Erik Eidt Sep 23 '21 at 18:28

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Registers are only word-addressable (with the 5-bit register number embedded in an instruction word). And register numbers are a separate address-space from memory. There's nowhere you can lw or sw to index into the register file on MIPS (unlike on a few 8-bit microcontrollers such as AVR with a memory-mapped register file).

Memory is byte-addressable, so every byte has 1 unique address. MIPS32 memory addresses are 32 bits wide, yes the width of a register such as $t0, so its address space includes 2^32 bytes = 4 GiB.

A word load on MIPS spans 4 bytes. e.g. a load from address 0x1000 gets the bytes at 0x100[0..3]. If you allow unaligned word loads (e.g. with a lwl/lwr pair), there are 4 different unaligned-word start addresses that overlap each byte. (This recent answer goes into more detail about MIPS lw / ARM ldr loading from 4 separate bytes as a single word.)

Peter Cordes
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  • Thank you, this clarified a lot of things. I just had a follow-up question (sorry I'm very new to this so I'm not quite familiar with certain terms)- what exactly does the term address-space mean? where is it? how is it stored? and 0x1000 is a memory address of one byte correct? and the lw command retrieves 4 bytes starting from this 0x1000 address? – anonimousse Sep 23 '21 at 09:44
  • @anonimousse: `0x1000` is an address. It doesn't imply anything about what size of load or store you can do to that address. Just like in C, you can do `*(char*) &my_int` to access the first byte (`char`) at the of an `int`. And yes, a MIPS "word" is 4 bytes like I said in my answer; a MIPS instruction-set manual should explain what `lw` (Load Word) does if you're not sure. – Peter Cordes Sep 23 '21 at 11:22
  • As for "address space", it's not "stored" anywhere, it's the set of addresses that can theoretically be used. There might not be RAM (or allocated virtual memory) backing any given address. Did you try google for terms you're not sure about? https://en.wikipedia.org/wiki/Address_space looks like it has a decent beginner-friendly introduction to the concept, although I just glanced at it. – Peter Cordes Sep 23 '21 at 11:25