How many cycles does it take to access the L1 cache and main memory i know it is dependent.
if L1, L2, L3 are missed, how many cycles does it take to access main memory ?
but i want to know approximate average cycles.
How many cycles does it take to access the L1 cache and main memory i know it is dependent.
if L1, L2, L3 are missed, how many cycles does it take to access main memory ?
but i want to know approximate average cycles.