Loop VHDL It does not work as expected

Question

After being yesterday and today I have managed to solve a few problems but I've gotten stuck again. When doing the counter I have put a loop so that it counts from 1 to 53 and then reset to zero again. The problem appears when to check that it works correctly I start the testbench and the signal is not updated at all.

-- Process incorporated in vhdl
entity semaforo is
Port ( sensor : in  STD_LOGIC;
       clk : in  STD_LOGIC;
       rst_n : in  STD_LOGIC;
       light_highway : out  STD_LOGIC_VECTOR (2 downto 0);
       light_farm : out  STD_LOGIC_VECTOR (2 downto 0));
 end semaforo;

architecture Behavioral of semaforo is

signal cuenta: std_logic_vector(6 downto 0):="0000000";

begin 

flip_flop: process (clk, rst_n)

begin

if (rst_n='0') then 

 light_highway <="001";

 light_farm <="100";

elsif (clk'event and clk='1') then 

 if (sensor='1') then   

  light_highway<="010";

 end if;

end if;

 end process;


contador : process (clk, rst_n)

begin

if rst_n = '0' then

  cuenta <= (others => '0');

elsif rising_edge(clk) then

  if sensor = '1' then

    if cuenta < 53 then

      cuenta <= cuenta + 1;

    else

      cuenta <= (others => '0');

    end if;  -- count/wrap

  end if;    -- clock enable

end if;      -- async reset/clock

 end process;

end Behavioral;

In the case that you remove the for and simply update the counter directly if it works but I need the counter to start adding up from the first time that sensor = '1' and that once the account started it does not stop (even if the sensor signal) until you reach the limit. Attached also capture of the testbench.

Just look around on SO: [How do you make vhdl counter that can count in tenths of a millisecond?](https://stackoverflow.com/questions/29027688/how-do-you-make-vhdl-counter-that-can-count-in-tenths-of-a-millisecond), [Counter inside FSM in VHDL](https://stackoverflow.com/questions/30302117/counter-inside-fsm-in-vhdl), [Implementing a counter in VHDL](https://stackoverflow.com/questions/42889830/implementing-a-counter-in-vhdl), etc... — JHBonarius, Dec 20 '17 at 19:23

EML · Answer 1 · 2017-12-21T08:34:54.753

1

This code won't compile. However, your basic problem is how processes work, and the loop. The process carries on executing until it suspends (in this case, at the end). When execution hits a variable assignment, the variable is updated immediately. When execution hits a signal assignment, the assignment is scheduled to take place at some point in the future, after the process suspends. Look up delta cycles and the scheduling model.

So, in this case, the entire loop is executed during one activation of the process, at a clock rising edge. Each scheduled ('non-blocking') assignment to account simply over-rides the previous scheduled assignment to account. The last assignment to account wins, so when we get to the end of the process, the scheduler has a single scheduled assignment: it assigns zero to account.

EDIT

I think you're just asking for a 6-bit counter, with an async reset, a count enable, and wrap-around. Generic code below. Note that this requires VHDL 2008 to read back the account output in order to increment it.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity E is
  port(
    clk     : in  std_logic;
    rst_n   : in  std_logic;
    sensor  : in  std_logic;
    account : out unsigned(5 downto 0));
end entity E;

architecture A of E is
begin
  counter : process (clk, rst_n)
  begin
    if rst_n = '0' then
      account <= (others => '0');
    elsif rising_edge(clk) then
      if sensor = '1' then
        if account < 53 then
          account <= account + 1;
        else
          account <= (others => '0');
        end if;  -- count/wrap
      end if;    -- clock enable
    end if;      -- async reset/clock
  end process;
end architecture A;

edited Dec 21 '17 at 08:34

answered Dec 20 '17 at 16:15

EML

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Thanks for your answer! I understand what you are saying but in such a case how would a counter that starts the count at the first instant in which sensor = '1', add up depending on each pulse and then add up if the sensor signal changes ? Basically I need to build the sensor so that some traffic lights change state in certain pulses. Sorry for the lack of clarity but I am new programming in vhdl as well as in the forum. – Anónimo salvaje Dec 20 '17 at 18:10
@Anónimo salvaje: 'add up if the sensor signal changes' doesn't really make sense. I'm assuming you mean 'only count if the sensor signal is set', in which case see the edit above. HTH. – EML Dec 21 '17 at 08:39
I would discourage the use of asynchronous reset and the use of `unsigned` at the entity port interface. I would advice initialization of `account` – JHBonarius Dec 21 '17 at 13:47
The choice of async vs sync reset depends on several factors. For Xilinx devices, Xilinx currently recommends sync, but not for particularly compelling reasons; their advice has changed over the years. See Keating&Bricaud for a fairly comprehensive comparison, or even Cummings. No problem with unsigned, particularly internal to a device; it's many years since external tools didn't understand unsigned. `account` is reset; it doesn't make sense to attempt any further sim-only initialisation. – EML Dec 21 '17 at 15:52
Thanks to all for the help. I attach images of my current testbench and what I hope to build to clarify it. I need that in the second 3 when sensor becomes 1 the counter count continuously up to 53 (unless there is a change in rst_n) so that after another process when for example account is 13 change the value of the semaphores. I'm sorry for the inconveniences https://ibb.co/nwqGaR https://ibb.co/dwU9vR – Anónimo salvaje Dec 21 '17 at 19:51
The sim looks good, but I'm afraid that your explanation of the problem isn't understandable, so we can't really help. If your English isn't good enough, you should draw a timing diagram, like the sim waveform, showing what outputs you expect when the controls change (you should always do that as part of your design anyway). – EML Dec 22 '17 at 08:16

score 0 · Answer 2 · answered Dec 21 '17 at 05:16

0

VHDL didn't have loop like c++. Delete loop statement. Every time CLK rising edge happen Your counter will count.

answered Dec 21 '17 at 05:16

Nader

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Loop VHDL It does not work as expected

2 Answers2