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I am building a cache simulator for a intel core i7 but have a hard time finding the detailed specifications for the L1, L2 and L3 cache (shared). I need the Cacheblock size, cache size, associativity and so on... Can anyone point me in the good direction?

Leeor
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Don
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1 Answers1

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Intel's Optimization guide describes most of the required specifications per architectural generation (you didn't specify which i7 you have, there are now several generations since Nehalem and up to Haswell).

Haswell, for e.g., would have - enter image description here

Note that if you're building a simulator, you'll want to have as many of these feature as possible parametrized. There are also many other considerations you'll need to take into account that are explained there (for e.g. inclusiveness, write-back/write-through protocols, cache coherency protocols, etc..)

Leeor
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  • The simulator isn't for public use, and is just for testing very basic principles so I won't be putting too much effort in the parameterisation. But thanks a whole lot!! – Don Dec 05 '13 at 17:21
  • @Don Can you guys take a look at this caching question? http://stackoverflow.com/questions/30555623/how-many-bits-are-in-the-address-field-for-a-directly-mapped-cache – committedandroider May 31 '15 at 16:53