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I am currently working on a project where I want to implement a bidirectional bus. For this project I was given an entity that I should not edit. This entity has two inout ports (sda and scl). I now want to write from the TestBench to the entity through the inout port sda. To do this I assign a value to to the signal that is connected to sda.

When I do this, I get the error that I have multiple sources for the unresolved signal sda. One is the assigned value and one is the entity itself. I do not understand how I can assign a value to this inout port without triggering this error.

Is there a quick explanation for this problem ? Otherwise what buzzwords are useful for searching a solution to this problem ?

My code for this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity i2c_slave_tb is
end i2c_slave_tb;

architecture arch of i2c_slave_tb is
-- signal declaration
-- sim signals

-- uut signals
signal sda: std_ulogic;
signal scl: std_ulogic;

begin  -- arch

  uut : entity work.i2c_slave
    port map (
    sda=>sda,
    scl=>scl
    );

  stim_gen :process 
  begin
    wait for 10 ns;
    sda<='1';
    wait;
  end process stim_gen;  

end arch;
Morten Zilmer
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user3155501
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1 Answers1

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The sda and scl signals are std_ulogic where the "u" stands for unresolved, meaning that there can be only one driver for the signal, since there is no resolution function attached to the type to determine the signal value in case of multiple drivers.

Change the type to std_logic for a type with standard resolution function, like:

signal sda: std_logic;
signal scl: std_logic;

You can look here for some description of "VHDL resolution function", or search it.

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Morten Zilmer
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