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I tried to implement an adder which is way faster then the average RCA. Therefore I used the XILINX library and found one easy adder called adsu8. I want to embed it into my recent VHDL code. but therefore I have to stick to the data type BIT and BIT_VECTOR. Now every time I synthesise there pops out a bunch of warnings like this:

:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- entity of module
entity rca_8bit is
Port ( OP_A : in  BIT_VECTOR (7 downto 0);
       OP_B : in  BIT_VECTOR (7 downto 0);
       ADDSUB : in  BIT;
       SUM : out  BIT_VECTOR (7 downto 0);
          FLAGS : out BIT_VECTOR (4 downto 0));
end rca_8bit;

-- architecture describes behavior of module
architecture behavioral of rca_8bit is
-- sub-module is declared
component adsu8
    port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
             B : in  STD_LOGIC_VECTOR (7 downto 0);
             CI : in BIT;
             S : out  STD_LOGIC_VECTOR (7 downto 0); 
             CO : out  BIT;
             OFL : out BIT);
end component;
-- some code to avoid the blackbox warning message of 
--  component adsu8 which is implemented from schematics  
attribute box_type : string; 
attribute box_type of adsu8 : component is "black_box"; 

-- additional wires std_logic
signal SIG_A,SIG_B,SIG_S : STD_LOGIC_VECTOR (7 downto 0); 

-- additional wires bit
signal  SIG_SUM : BIT_VECTOR (7 downto 0);
signal  SIG_FLAGS :  BIT_VECTOR (4 downto 0);
signal  SIG_CO,SIG_OFL : BIT;


begin
-- instantiate and do port map
AS8 : adsu8 port map (SIG_A,SIG_B,ADDSUB,SIG_S,SIG_CO,SIG_OFL);

-- convert and forward std_logic to bit
SIG_A <= to_stdlogicvector(OP_A);
SIG_B <= to_stdlogicvector(OP_B);
SIG_SUM <= to_bitvector(SIG_S);

-- assign result
SUM <= SIG_SUM;
-- generate flags
SIG_FLAGS(0) <= SIG_SUM(7) xor SIG_FLAGS(1);            -- S (N xor V)
SIG_FLAGS(1) <= SIG_OFL;                                -- V
SIG_FLAGS(2) <= SIG_SUM(7);                             -- N (MSB = 0)
SIG_FLAGS(3) <= '1' when SIG_SUM = "00000000" else '0'; -- Z
SIG_FLAGS(4) <= SIG_CO;                                 -- C
-- assign flags
FLAGS <= SIG_FLAGS;

end behavioral;

I am not this experienced in VHDL but also not that less. But this problem confuses me and causes headache. I am grateful for any solution or information in the right direction.

Thanks in advance and best regards

Tobi

Tobias Junge
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    It's not an answer, but do you really need to use a schematic module for a simple add/subtract unit? In my experience any advantage of using schematic mode is far outweighed by the problems you always seem to have to work through when using the entities created by it. – scary_jeff Aug 20 '15 at 16:03
  • The simple RCA adder included in the Xilinx devices is very fast. Therefore Xilinx implemented carry-chains to speed RCAs and other logic up. Other solutions maybe faster than the classic RCA, but the break-even point is beyond several dozens of bits. – Paebbels Aug 20 '15 at 17:02
  • In my application speed is the key and the adder is determined as bottleneck. I rather want to implement an available module than implement a complex carry chain. Is there a way to re-assign the datatypes? Any other workaround is welcome. – Tobias Junge Aug 20 '15 at 17:35
  • Again this might not be helpful, but maybe someone could spot why your VHDL adder was not performing so well if you posted the code. There's no reason I'm aware of that the tools shouldn't infer the use of the dedicated carry chain logic from a simple VHDL `c <= a + b`. – scary_jeff Aug 21 '15 at 08:11
  • It is not cause, I am to lazy to implememt a carry chain in addtion with another sort of adder (csa, claa...). But now I will do to get rid of this issue. Cheer at you all for trying to help! Best regards. – Tobias Junge Aug 21 '15 at 17:10

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