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Questions tagged [hardware-design]

15 questions
4
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1 answer

Cache request in Forth CPU

In the RAM of the computer a longer program is stored, written in the Forth programming language. It contains of three subfunctions and takes too many bytes for storing them in the first-level-cache of the CPU. A caching strategy is needed which…
Manuel Rodriguez
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Verilog: wait for module logic evaluation in an always block

I want to use the output of another module inside an always block. Currently the only way to make this code work is by adding #1 after the pi_in assignment so that enough time has passed to allow Pi to finish. Relevant part from module pLayer.v: Pi…
cie
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Multiplexer in vhdl with structural design

I am totally new to VHDL and I want to implement the following MUX for a logical implication S0 => S1 without using other gates. I want to use structural design, but one of my main problems is that I don't understand how to map the ports correctly…
Landau
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How to implement a schematic in vhdl code and converting the datatypes from std_logic to bit

I tried to implement an adder which is way faster then the average RCA. Therefore I used the XILINX library and found one easy adder called adsu8. I want to embed it into my recent VHDL code. but therefore I have to stick to the data type BIT and…
Tobias Junge
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2 answers

Unknown Wrong result when simulating Verilog design in modelsim

Design: //structural description of 74151 module s_74151(VCC, GND, D0, D1, D2, D3, D4, D5, D6, D7, A, B, C, STROBE, Y, W); input D0, D1, D2, D3, D4, D5, D6, D7; //data inputs input STROBE; //enable input A, B, C; //Data select output Y, W;…
mj1261829
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Using Generate in Vhdl

I have following piece of code in Vhdl now I want to redirect this signal S1 conditionally to the output port, I will be gratful if someone can guide me through this. Gen: for index in 0 to 4 generate signal s1 : ARRAY_TYPE; --- array of (0 to 7)…
user1107855
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Hardware design a 3 binary numbers adder

I want to design a binary full adder to add 3 binary numbers , a typical cell of this adder would look like this Can someone explain why we have 2 carries to the next bit ? regards
Hussein Hammoud
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1 answer

Can I use openCV libraries with Catapult C?

My final aim is a face/object detection and general image processing application on a Altera DE2 FPGA. I am using Catapult C to program the FPGA (so I am using C code, not Verilog or VHDL). My question is if Catapult C supports openCV libraries,…
Chris
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How to manage uninitialized input signals

I would like to know your opinion on how to test and manage input signals of a component that are 'U', 'X', '-', ... For example, if I want the output to be 'X' for all non-valid inputs, where at least one bit of the input isn't '0' or '1': entity…
Mat
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Truncated ternary multipliers ulp error calculation

the following paper provides some insides about truncated ternary multipliers: https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-cdt.2013.0133 , I understand the concept explained here in general but there is one detail related to the…
Rhysio Eren
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stm32wb, nucleo-wb55, sensor, hardware

I am using nucleo-wb55 development board with STM32WB55 processor. I want to connect sensors like IIS3DWB, STTS22H to this board. How can I go about connecting the modules of these sensors to nucleo-wb55?
AliEkber
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Why are inner components not being executed

So, i've created a hierarchical desing of components in VHDL. The top level entity for now is the following. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --This component takes 2 numbers written in scientific notation and…
user3013172
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Can two chips take turns accessing two memory banks?

Suppose you have two chips - for concreteness, say a CPU and a video chip - both of which want to access memory at the maximum bandwidth of which the memory is capable. Say each video frame is X bytes, the CPU wants to write X bytes to generate the…
rwallace
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Hardware for "A div B" with A and B fixed point

I need a way to compute how many times a fixed point number B is contained into a fixed point number A. Something like integer division but on non-integer operands. I need to design an hardware block for this operation. My first guess is to use…
KBowser
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Data hazards in hardware platforms

I have got a list of 2 types of hazards: 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt I am not able to understand the intuition…
brainstorm12
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